1. Field of the Invention
The present invention generally relates to electronic memories and, more particularly, to decoder/driver circuits for static memories utilizing the Harper PNP cell.
2. Description of the Prior Art
Electronic memory circuits have been known for many years. Such memory circuits have employed a wide variety of types of circuits and circuit elements in order to store information in some way, such as by storage of charge in a capacitive element or the use of a bistable circuit or element. Such a bistable element can take the form, for example, of the well-known flip-flop circuit, where a pair of transistors are cross-coupled in such a way that when one transistor is turned on, the other will be forced off, or a magnetizable core or other element or domain which can be selectively magnetized into one of at least two distinct states.
Each of these memory types, categorized by the type of memory cell employed, has distinct advantages and disadvantages with respect to the other types of memory and each type will typically be applied where the advantages can be best utilized. In particular, static random access memories using bistable circuits constructed from bipolar transistors are typically used in cache memories and central processing units due to their characteristically high speed. The access cycle times of such devices can be as short as 3 ns, or more than an order of magnitude faster than dynamic RAMs, due largely to their lack of need for refresh and inherently faster operation of sense amplifiers since detection of data in a bistable circuit of a static RAM is far easier than detection of a minuscule amount of electrical charge in a capacitive memory cell of a dynamic RAM.
While static RAMs use many more circuit elements per storage cell than dynamic RAMs and are therefore limited to a smaller number of storage cells possible on a chip of a given size, increased numbers of storage cells present some problems in design due to the fact that a typical storage cell will have a circuit including at least a pair of cross-coupled transistors, one of which will be conductive at any given time. Reduction in average cell standby current through the conductive transistor of each cell typically increases susceptibility of the cell to soft errors, due, for instance, to disruption of charge distribution caused by alpha particles.
One particularly successful memory cell circuit design is the Harper PNP cell, illustrated in FIGS. 1a-1c. One advantage of the Harper PNP cell is that the standby current can be reduced to about 5 microamperes per cell and still result in a reasonable soft error rate. This feature is provided with a very simple and compact circuit which can be integrated at high density on the memory chip. The compactness results from the fact that it includes two cross-coupled pairs of transistors, each of which includes a PNP transistor and NPN transistor. The two transistors of each pair can be merged to form a PNPN silicon controlled rectifier (SCR) device. The operation of this circuit will be described in more detail below.
In recent years, there has been an interest in increasing the memory capacity of all types of memory devices, including static memory devices. Some particular problems are encountered in doing so in static RAMs because the size of each memory cell on the chip is much larger than in dynamic RAMs due to the use of a greater number of circuit elements in each memory cell. While the problem is of greater complexity than is relevant to an understanding of the present invention, the basic elements of the problem concern word line resistance and capacitance.
Word line capacitance is generally a function of word line length and increased capacitance tends to slow the switching function of the word line driver used for selection. Increased word line length can also increase susceptibility to noise. Therefore, there is a practical limit on the length of the word lines which may be employed, limiting the number of cells which can physically be placed along that length.
Bistable static memory cells also inherently draw current over the word lines regardless of the data stored therein, due to the nature of the bistable circuit operation. While this current can be reduced to low levels during deselected operation, possible voltage drops along the word line during both selected and deselected operation is not negligible and must be considered during memory device design.
For these reasons, the number of cells which can be attached to a given word line or lines associated with a single word line driver is typically limited to 128 or 256 cells. Since selection of memory cells for a write or read operation in any RAM is a joint function of both word lines and bit lines, static RAMs cannot be expanded by increasing the number of bit lines beyond the practical limit imposed by the number of cells which can be driven by a single word line driver. Therefore, any increase in memory capacity must be accompanied by a directly proportional increase in the number of word line drivers.
The word line drivers also typically perform a decoding function and, for this reason, are often referred to as word line decoder/drivers. Typically, the circuit providing the decoding function will include a plurality of parallel connected transistors to which address signals are applied. One or more of these input transistors will be conductive at all times except when the cell is selected for a read or write operation. A resistor is placed in series with the collectors of these parallel connected input transistors in order to develop a voltage which is then used to control the transistors driving the word line. While the resistance of this series resistor might be increased to limit current through the input transistors during deselected periods, such a possibility is limited by the fact that the resistor must also supply the base current for the word line driver circuit when the driver is selected and the fact that increase of resistor value will decrease the voltage swing available when the driver is switched from a deselected state to a selected state or vice-versa. Reduction of this voltage swing also tends to decrease noise margins and increase susceptibility to errors due to electrical noise. Increase of this resistance also tends to decrease switching speed.
The use of a fixed resistor causes some further problems since, as indicated above, the resistor must supply the base current for the word line driver transistors. As a practical matter, the word line driver transistors are subject to variations in gain, .beta., due to unavoidable variations in the manufacturing process consistent with economy and good device yield. Since a fixed resistor can only supply a fixed base current to the word line driver transistors during selection periods, the variations in .beta. of the word line driver transistors may result in significant difference in the current and voltage applied to the memory cells during write and read operations, thus potentially reducing operational and noise margins of the memory device.
Further, to reduce word line length, word line driver circuits are usually placed in a central location on the chip and a node connecting the base nodes of a plurality of word line driver transistors is formed. This node will have a capacitance which is not negligible and the time constant associated with this capacitance and the series input resistance will reduce switching speed for a given capacitance of the node if the resistance is large.
Also, a fixed resistance does not allow for either the word line or the base node of the word line driver transistors to be clamped to a power supply voltage without saturation of the word line driver transistors or transistors in the input circuit, respectively. This design consideration imposes a trade-off between noise immunity and switching speed. For this reason, it is often necessary to provide some voltage regulation means to assure adequate performance of the memory device.
Because the series resistor is subject to these conflicting design constraints, practical word line drivers typically draw a greater current and consume more power than the memory cells to which they are connected. For this reason, when the memory capacity is made large with a proportionate increase in the number of word line drivers, the power consumed by the drivers for, say, a static RAM of 128K capacity (which would thus have a minimum of 512 or 1024 word line drivers), even in the standby or deselected state, can reach a value in excess of 40% of the total power consumed by the memory device. This amount of power consumption leads to problems of heat dissipation and may require expensive cooling arrangements to be provided. Even if the problem of heat dissipation could be satisfactorily and economically solved, the prior art does not provide any means of avoiding the trade-off between power consumption and performance, particularly in the areas of speed and noise immunity. In this regard, it is to be understood that while these problems are especially critical in static RAMs, the same problems are also encountered in other types of memory devices, as well.
Therefore, a need exists in the prior art to provide a circuit which will allow standby power to be reduced in a word line driver circuit for a memory while maintaining or improving switching speed and noise immunity.